Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 449

0
Field
Reset
R/W
Addr (IMMR & 0xFFFF0000) + 0x100 (BR0), 0x0x108 (BR1), 0x110, (BR2), 0x118 (BR3), 0x120 (BR4),
16 17
Field BA
Reset
R/W
Addr (IMMR & 0xFFFF0000) + 0x102 (BR0), 0x10A (BR1), 0x112, (BR2), 0x11A (BR3), 0x122 (BR4),
After reset, BR0 has different default values than other BRx registers until the first write to OR0.
0
Field
Reset
R/W
Addr
16 17
Field BA
Reset x
R/W
Addr
1
Because at reset the base address value of BR0 is unknown, to ensure proper operation, program BR0 before OR0.
2
The reset value of PS depends on the boot port size (BPS) field of the hard reset configuration word.
3
The reset value of V depends on the boot disable (BDIS) field of the hard reset configuration word.
Freescale Semiconductor
xxxx_xxxx_xxxx_xxxx
0x128 (BR5), 0x130 (BR6), 0x138 (BR7)
19 20 21 22
AT PS —
xxxx_xxxx_xx00_0000
0x12A (BR5), 0x132 (BR6), 0x13A (BR7)
Figure 15-5. Base Registers (BR x )
xxxx_xxxx_xxxx_xxxx
(IMMR & 0xFFFF0000) + 0x100
19 20 21 22
AT PS —
2
xxx 0
(IMMR & 0xFFFF0000) + 0x102
Figure 15-6. BR0 Reset Defaults
MPC885 PowerQUICC Family Reference Manual, Rev. 2
BA
R/W
23 24 25 26
WP MS
R/W
BA
1
R/W
23 24 25 26
WP MS
0 00
R/W
Memory Controller
15
30 31
— V
15
30 31
— V
3
00_000
15-9