Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 953

The USB and SCCs CIPR bit positions are not changed according to their relative priority (as determined
by CICR[SCxP] and CICR[SPS]). If the error vector is issued in the CIVR, this means that no CIPR bits
were cleared when CIVR[IACK] was set.
35.5.3 CPM Interrupt Mask Register
Each bit in the read/write CPM interrupt mask register (CIMR) corresponds to a CPM interrupt source
indicated in CIPR. The CIPR and CIMR are shown in
enabled by setting the corresponding CIMR bit. Even if an interrupt is masked, the corresponding CIPR
bit is set when an interrupt condition occurs, but the interrupt request is not passed to the core.
If a CPM interrupt source is requesting interrupt service when its CIMR bit is cleared, the request stops.
If the bit is set later, the core processes previously pending interrupt requests according to priority.
The CIMR[USB,SCCx] bit positions are unaffected by the relative priority programmed in the
configuration register, CICR.
35.5.4 CPM Interrupt In-Service Register (CISR)
Each bit in the CPM interrupt in-service register (CISR) corresponds to a CPM interrupt source. The CISR,
CIPR, and CIMR are shown in
when the core acknowledges the interrupt by setting CIVR[IACK]. An interrupt service routine must clear
the corresponding CISR bit after servicing is complete. If an event register exists for this peripheral, its
bits would normally be cleared. Write ones to clear CISR bits; writing zeros has no effect.
Bits set in this register indicate which interrupt requests are in progress for each CPM interrupt source.
More than one CISR bit can be set if higher priority CPM interrupts are allowed to interrupt lower priority
level interrupts within the same CPM interrupt level. For example, the TIMER1 interrupt routine could
interrupt the TIMER2 interrupt handler. See
CISR[TIMER1] and CISR[TIMER2] are set.
The USB and SCCs CISR bit positions are not affected by the relative priority between one another. If the
error vector is taken, no CISR bit is set. All undefined CISR bits return zeros when read. The extent to
which CPM interrupts can interrupt one another is controlled by selectively clearing the CISR. A new
interrupt is processed if it has a higher priority than the highest priority interrupt having its CISR bit set.
Thus, if an interrupt routine sets the external interrupt enable bit in the core (MSR[EE]) and clears its CISR
bit at the beginning of the interrupt routine, a lower priority interrupt can interrupt a higher one if the lower
priority interrupt has higher priority than any other CISR bits that are currently set. Therefore, the interrupt
service routine should clear its CISR bit at the end.
35.5.5 CPM Interrupt Vector Register (CIVR)
The CPM interrupt vector register (CIVR) is used to identify an interrupt source. The core uses the IACK
bit to acknowledge an interrupt. CIVR can be read at any time. This register is affected by HRESET and
SRESET.
Freescale Semiconductor
Figure 35-4. In a vectored interrupt environment, the CPIC sets a CISR bit
Section 35.2.3, "Nested Interrupts."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure 35-4. An interrupt is masked by clearing and
CPM Interrupt Controller
During this time, both
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