Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 892

Powerquicc family

Table of Contents

C Controller

TCOUNT Hword Tx internal byte count

As programmed in I2C_BASE. The default value is IMMR + 0x3C80. See

Normally, these parameters need not be accessed.

Figure 32-11

shows the RFCR/TFCR bit fields.

describes the RFCR/TFCR bit fields.

Reserved, should be cleared.

Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on the fly,

it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the

beginning of the next BD. See

01 Modified little-endian.

1x Big-endian or true little-endian.

AT[1–3] Address type 1–3. Contains the user-defined function code value used during the SDMA channel

memory access. AT0 is always driven high to identify this channel access as a DMA-type access.

Table 32-6. I

C Parameter RAM Memory Map (continued)

Word Rx temp. Reserved for CPM use.

Word Tx internal state. Reserved for CPM use.

Word Tx internal data pointer

in the buffer to be accessed.

Hword TxBD pointer. Points to the next descriptor that the transmitter transfers data from

when it is in an idle state or to the current descriptor during frame transmission. After

a reset or when the end of the descriptor table is reached, the CPM initializes TBPTR

to the value in TBASE. Most applications should not write TBPTR, but it can be

modified when the transmitter is disabled or when no transmit buffer is used.

decremented with every byte read by the SDMA channels.

Word Tx temp. Reserved for CP use.

C/SPI relocation, see

I2C Base + 04 (RFCR)/I2C Base + 05 (TFCR)

Figure 32-11. I

C Function Code Registers (RFCR/TFCR)

Table 32-7. RFCR/TFCR Field Descriptions

Appendix A, "Byte Ordering."

MPC885 PowerQUICC Family Reference Manual, Rev. 2

is updated by the SDMA channels to show the next address

is a down-count value initialized with TxBD[Data Length] and

Section 18.7.3, "Parameter

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