Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 627

Figure 20-18 shows SIMODE[FE] behavior with SIMODE[CE] set and no frame sync delay.
CE=1
L1CLK
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
Figure 20-18. Falling Edge (FE) Effect When CE = 1 and x FSD = 00
Freescale Semiconductor
Rx Sampled Here
Rx Sampled Here
MPC885 PowerQUICC Family Reference Manual, Rev. 2
The L1ST is Driven from Sync.
Data is Driven from Clock Low.
L1ST is Driven from Clock High.
Both Data Bit-0 and L1ST are
Driven from Sync.
L1ST and Data Bit-0 is Driven
from Clock Low.
Serial Interface
xFSD=00
(FE=0)
(FE=0)
(FE=1)
(FE=1)
20-21