Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 290

Powerquicc family

Table of Contents

System Interface Unit

PCMCIA host adapter module supports slot with eight memory or I/O windows

IEEE 1149.1 test access port

System Configuration and Protection

The MPC885 incorporates many system functions that normally must be provided in external circuits. The

following features provide maximum system safeguards against hardware and/or software faults:

System configuration—Allows control of show cycle operation, and part and mask number

Bus monitor—Monitors the TA response time for bus accesses initiated by internal masters. TEA

is asserted if the TA response limit is exceeded. The bus monitor measures time between TS and

any termination of the bus cycle, including TA, TEA, and RETRY.

Software watchdog timer (SWT)—Asserts a reset or nonmaskable interrupt (NMI) that is selected

by the system protection control register (SYPCR) if software fails to service this timer after a

certain period. After system reset, the timer, if enabled, selects a maximum time-out period and

asserts SRESET or NMI (system reset interrupt) if the time-out is reached. This timer can be

disabled or its time-out period can be changed in SYPCR. Once SYPCR is written, it cannot be

written again until a system reset.

Periodic interrupt timer (PIT)—Generates periodic interrupts for use with a real-time operating

system (RTOS) or the application software. The PIT is clocked by the PITCLK clock and can be

disabled if it is not needed.

Timebase counter—Provides a timebase reference for the operating system or application

software. This 64-bit timebase counter is defined by the PowerPC architecture and has two

independent reference registers that generate a maskable interrupt when the programmed value in

one of the registers is reached. The associated bit in the timebase status and control register

(TBSCR) is set for the reference register that generated the interrupt. The timebase is clocked by

the TMBCLK clock.

Decrementer—Provides a decrementer register/interrupt clocked at the timebase frequency. This

32-bit decrementing counter is defined to be clocked by TMBCLK. When it is driven by a 4-MHz

oscillator the period for the decrementer is 4,295 seconds (approximately 71.6 minutes).

Freeze support—The SIU determines whether the software watchdog timer, PIT, timebase, and

decrementer should continue to run in freeze mode.

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Freescale Semiconductor