Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 646

Powerquicc family

Table of Contents

Serial Interface

UART Baud Rate Examples

For synchronous communication using the internal BRG, the BRGO output clock must not exceed the

system frequency divided by 2. So, with a 25-MHz system frequency, the maximum BRGO rate is 12.5

MHz. Program the UART to 16× oversampling when using the SCC as a UART. Rates of 8× and 32× are

also available. Assuming 16× oversampling is chosen in the UART, the maximum data rate is 25 MHz ÷

16 = 1.5625 Mbps. Keeping the above in mind, use the following formula to calculate the bit rate based

on a particular BRG configuration for a UART:

async baud rate = (BRGCLK or CLK2 or CLK6) ÷ (1 or 16 according to BRGCx[DIV16]) ÷ (clock

divider + 1) ÷ (8, 16, or 32 according to GSMR_L[TDCR, RDCR] in the general SCC mode register

lists typical bit rates of asynchronous communication. Notice that here the internal clock rate

is assumed to be 16× the baud rate; that is, GSMR_L[TDCR] = GSMR_L[RDCR] = 0b10.

Table 20-14. Typical Baud Rates for Asynchronous Communication

For synchronous communication, the internal clock is identical to the baud rate output. To get the preferred

rate, select the system clock according to the following:

sync baud rate = (BRGCLK or CLK2 or CLK6) ÷ (1 or 16 according to BRGCx[DIV16]) ÷ (clock divider

For example, to get a rate of 64 kbps, the system clock can be 24.96 MHz, DIV16 = 0, and the clock

divider = 389.

MPC885 PowerQUICC Family Reference Manual, Rev. 2

System Frequency

Freescale Semiconductor