Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 451

Option Registers (OR x )
15.4.2
The option registers (OR0–OR7), shown in
address bus comparison. It also includes all GPCM parameters.
0
Field
Reset
R/W
Addr (IMMR & 0xFFFF0000) + 0x104 (OR0), 0x10C (OR1), 0x114 (OR2), 0x11C (OR3), 0x124 (OR4), 0x12C
16 17 18
Field AM ATM
Reset
R/W
Addr
At reset, OR0 has specific default values and is read-only, as shown in
becomes R/W.
0
Field
Reset
R/W
Addr
16 17
Field AM ATM
Reset 0 000
R/W
Addr
Freescale Semiconductor
Figure
xxxx_xxxx_xxxx_xxxx
(OR5), 0x134 (OR6), 0x13C (OR7)
19 20 21
CSNT/SAM ACS/G5LA,G5LS BIH
xxxx_xxxx_xxxx_xxx0
(IMMR & 0xFFFF0000) + 0x106
Figure 15-7. Option Registers (OR x )
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x104 (OR0)
19 20 21 22
CSNT/ ACS/G5LA,
SAM G5LS
1 11
(IMMR & 0xFFFF0000) + 0x106
Figure 15-8. OR0 Reset Defaults
MPC885 PowerQUICC Family Reference Manual, Rev. 2
15-7, contain the address and address type mask bit for
AM
R/W
22 23 24 27
SCY
R/W
Figure
AM
R
23 24 27
BIH SCY
1 1111
R
Memory Controller
15
28 29 30 31
SETA TRLX EHTR —
15-8. After reset, OR0
15
28 29 30 31
SETA TRLX EHTR —
0 1 0 0
15-11