Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 596

SDMA Channels and IDMA Emulation
IDMAx BD Base
Address (IBASE)
Source Device or
Buffer 0
Source Device or
Buffer 1
Source Device or
Buffer 2
•
•
•
Source Device or
Buffer n
An IDMA descriptor breaks down as follows:
• The half word at (offset + 0) is the status-and-control field.
• The byte at (offset + 2) is the destination function code register (DFCR). See
"Function Code Registers—SFCR and DFCR."
• The byte at (offset + 3) is the source function code register (SFCR). See
"Function Code Registers—SFCR and DFCR."
• The word at (offset + 4) is the buffer length, containing the number of bytes for transfer. It must be
greater than zero.
• The word at (offset + 8) points to the beginning of the source buffer in internal or external memory.
— When the source is a peripheral, this field is ignored in single-address mode. In dual-address
mode, this field contains the peripheral address.
• The word at (offset + 0xC) points to the beginning of the destination buffer in internal or external
memory.
— When the destination is a peripheral, this field is ignored in single-address mode. In
dual-address mode, this field contains the peripheral address.
19-10
BD 0
BD 1
BD 2
•
•
•
BD n
Figure 19-7. IDMA x Channel's BD Table
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Destination Device or
Buffer 0
Destination Device or
Buffer 1
Destination Device or
Buffer 2
•
•
•
Destination Device or
Buffer n
Section 19.3.4.1,
Section 19.3.4.1,
Freescale Semiconductor