Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 925

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Read Path
To
Write Path
From
Output
Latch
TXD1
From SCC1
Figure 34-6. Block Diagram for PA14 (True for all Open-Drain Port Signals)
34.3
Port B
All port B signals can be open-drain. They are configured independently as general-purpose I/O signals if
the corresponding bit in the PBPAR is cleared and they are configured as dedicated on-chip peripheral
signals if the corresponding PBPAR bit is set. When configured as a general-purpose I/O signal, the signal
direction of that signal is determined by the corresponding control bit in the PBDIR. The port I/O signal
is configured as an input if the corresponding PBDIR bit is cleared and it is configured as an output if the
corresponding PBDIR bit is set. All PBPAR bits and PBDIR bits are cleared by hardware reset, thus
configuring all port B signals as general-purpose inputs.
B is shared with the PIP, which is described in
If a port B signal is selected as a general-purpose I/O signal, it can be accessed through the PBDAT where
data is stored in an output latch. If a port B signal is configured as an output, the output latch data is gated
onto the port signal. When PBDAT is read, the port signal itself is read.
All port B signals can have multiple configurations, which include on-chip peripheral functions for
2
UTOPIA, SPI, I
C, SMCs, and the TDMs. Port B is also multiplexed with the PIP, which can implement
fast parallel interfaces. For a description of the dedicated PIP signal functions, see
Interface Port (PIP)."
Port B provides the PHY address signals for multi-PHY operation and one of the UTOPIA cell-available
control signals. In master mode, PB15 acts as the TxClav input signal; in slave mode (split bus mode
only),PB15 acts as the RxClav output signal.
UTOPIA multi-PHY operations use port B for RxAddr [4:0] and TxAddr [4:0] signals.The number of
active PHY address signals is programmed in UTMODE; for further information see "UTOPIA Mode
Register (UTMODE)" in
Freescale Semiconductor
0
EN
1
16-Bits
PADIR
0
MUX
1
EN
Chapter 33, "Parallel Interface Port (PIP)."
Chapter 43, "UTOPIA Interface."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
0
MUX
MUX
1
EN
EN
EN
16-Bits
PAPAR
Table 34-6
describes port B signal options. Port
Parallel I/O Ports
EN
RXD1/PA14
Open
Drain
Pin
Control
16-Bits
PAODR
Chapter 33, "Parallel
34-7

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