Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 16

Paragraph
Number
13.1 Features .......................................................................................................................... 13-1
13.2 Bus Transfer Overview .................................................................................................. 13-1
13.3 Bus Interface Signal Descriptions.................................................................................. 13-2
13.4 Bus Operations............................................................................................................... 13-6
13.4.1 Basic Transfer Protocol.............................................................................................. 13-6
13.4.2 Single-Beat Transfer .................................................................................................. 13-6
13.4.2.1 Single-Beat Read Flow .......................................................................................... 13-7
13.4.2.2 Single-Beat Write Flow ....................................................................................... 13-10
13.4.3 Burst Transfers......................................................................................................... 13-14
13.4.4 Burst Operations ...................................................................................................... 13-14
13.4.5 Alignment and Data Packing on Transfers .............................................................. 13-23
13.4.6 Arbitration Phase ..................................................................................................... 13-25
13.4.6.1 Bus Request (BR) ................................................................................................ 13-26
13.4.6.2 Bus Grant (BG).................................................................................................... 13-26
13.4.6.3 Bus Busy (BB)..................................................................................................... 13-27
13.4.6.4 External Bus Parking ........................................................................................... 13-29
13.4.7 Address Transfer Phase-Related Signals ................................................................. 13-29
13.4.7.1 Transfer Start (TS) ............................................................................................... 13-29
13.4.7.2 Address Bus ......................................................................................................... 13-30
13.4.7.3 Transfer Attributes ............................................................................................... 13-30
13.4.7.3.1 Read/Write (RD/WR) ...................................................................................... 13-30
13.4.7.3.2 Burst Indicator (BURST)................................................................................. 13-30
13.4.7.3.3 Transfer Size (TSIZ)........................................................................................ 13-30
13.4.7.3.4 Address Types (AT) ......................................................................................... 13-30
13.4.7.3.5 Burst Data in Progress (BDIP) ........................................................................ 13-33
13.4.8 Termination Signals ................................................................................................. 13-33
13.4.8.1 Transfer Acknowledge (TA) ................................................................................ 13-33
13.4.8.2 Burst Inhibit (BI) ................................................................................................. 13-33
13.4.8.3 Transfer Error Acknowledge (TEA).................................................................... 13-33
13.4.8.4 Termination Signals Protocol .............................................................................. 13-33
13.4.9 Memory Reservation................................................................................................ 13-35
13.4.9.1 Cancel Reservation (CR) ..................................................................................... 13-35
13.4.9.2 Kill Reservation (KR).......................................................................................... 13-36
13.4.10 Bus Exception Control Cycles................................................................................. 13-37
13.4.10.1 RETRY ................................................................................................................ 13-38
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Contents
Title
Chapter 13
External Bus Interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor