Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 292

System Interface Unit
Name
GPL_A0/GPL_B0
OE/GPL_A1/GPL_B1
GPL_A[2:3]/GPL_B[2:3]/CS[2:3]
ALE_B/DSCK/AT1
IP_B[0:1]/IWP[0:1]/VFLS[0:1]
IP_B2/IOIS16_B/AT2
IP_B3/IWP2/VF2
IP_B4/LWP0/VF0
IP_B5/LWP1/VF1
IP_B6/DSDI/AT0
IP_B7/PTR/AT3
TDI/DSDI
TCK/DSCK
TDO/DSDO
OP2/MODCK1/STS
OP3/MODCK2/DSDO
10.4 Programming the SIU
The following sections describe registers used for programming the SIU.
10.4.1 Internal Memory Map Register (IMMR)
The internal memory map register (IMMR) is an SPR that identifies specific devices and the internal
memory map base address. Using mfspr, software can read IMMR to determine the location and
availability of any on-chip system resource. ISB can be written by mtspr, but PARTNUM and
MASKNUM are mask-programmed and cannot be changed.
0
Field
Reset
R/W
16
Field
Reset
R/W
SPR
10-4
Table 10-1. Multiplexing Control (continued)
Dynamically active depending on the machine (UPMA or UPMB) assigned to
control the required slave.
Dynamically active depending on the machine (GPCM, UPMA, or UPMB)
assigned to control the required slave.
GPL_A[2:3]/GPL_B[2:3]: Dynamically active depending on the machine (UPMA
or UPMB) assigned to control the required slave.
GPL_A[2:3]/CS[2:3]: Programmed in the SIUMCR.
Programmed in the SIUMCR and hard reset configuration. See
"Hard Reset Configuration Word."
At power-on reset, this functions as MODCK[1:2]. Otherwise, programmed in the
SIUMCR and hard reset configuration.
Set by reset configuration
PARTNUM
000_0000
R
Figure 10-2. Internal Memory Map Register (IMMR)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Pin Configuration Control
ISB
R/W
23 24
MASKNUM
Value depends on the mask revision
638
Section 11.3.1.1,
15
31
R
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