Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 568

Communications Processor
Figure 18-1 is a block diagram of the CP.
INSTRUCTION STORAGE
RAM
ROM
Sequencer
Scheduler
Service Requests
Figure 18-1. Communications Processor (CP) Block Diagram
18.2 Communicating with the Core
The CP communicates with the core in the following ways:
• By exchanging parameters using the dual-port RAM.
• By executing special commands that are issued by the core through the CP command register
(CPCR).
• By generating interrupts using the CPM interrupt controller (CPIC).
• By letting the core read the CPM status/event registers at any time.
18.3 Communicating with the Peripherals
The CP uses the peripheral bus to communicate with the peripherals. The universal serial bus (USB) and
the serial communications controllers (SCCs) have separate receive and transmit FIFOs. The USB and
SCC2–SCC4 receive and transmit FIFOs are 16 bytes each. The serial management controllers (SMCs),
serial peripheral interface (SPI), and I
characters.The parallel interface port (PIP) is a single register interface.
18-2
Decoder
Register
File
•
Development
•
Support
•
2
C are all double-buffered, creating effective FIFO sizes of two
MPC885 PowerQUICC Family Reference Manual, Rev. 2
PROCESSING UNITS
Multiplier/
Accumulator
Cyclic
Redundancy
DMA
Check
Arithmetic
Logic Unit
Dual-Port
RAM
Peripheral
Interface
Peripheral
Bus
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