Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 591

Table 19-2 describes the SDCR bit settings.
Bits Name
0–16 — Reserved, should be cleared.
17 FRZ Freeze. Recognize or ignore the freeze signal. If configured to respond to the freeze signal, the
SDMA controller negates BR until freeze is negated or a reset occurs.
00 SDMA channels ignore the freeze signal.
01 Reserved.
10 SDMA channels respond to a freeze on the next bus cycle.
11 Reserved.
19–24 — Reserved, should be cleared.
25 — Reserved, should be set to 1.
26–31 — Reserved, should be cleared.
19.2.2 SDMA Status Register (SDSR)
Shared by all SDMA channels, the SDMA status register (SDSR) reports bus errors. When the SDMA
controller recognizes an event, it sets the corresponding event bit in the SDSR. SDSR bits are cleared by
writing ones; writing zeros has no effect.
0
Field SBER
Reset
R/W
Addr
This register is affected by HRESET and SRESET.
.
Bits Name
0 SBER SDMA channel bus error. Indicates an error caused the SDMA channel to terminate during a read or
write cycle. The SDMA bus error address can be retrieved from the SDMA address register (SDAR).
1–7 — Reserved
19.2.3 SDMA Mask Register (SDMR)
The read/write SDMA mask register (SDMR) has the same bit format as SDSR; see above
a bit in the SDMR is set, the corresponding interrupt in the SDSR is enabled; if the bit is cleared, the
corresponding interrupt is masked. Reset clears SDMR. Its internal address (IMMR offset) is 0x90C. This
register is affected by HRESET and SRESET.
Freescale Semiconductor
Table 19-2. SDCR Bit Settings
Figure 19-4
1
0000_0000
IMMR + 0x908
Figure 19-4. SDMA Status Register (SDSR)
Table 19-3
Table 19-3. SDSR Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SDMA Channels and IDMA Emulation
Description
shows the register format.
—
R/W
describes the SDSR bit settings.
Description
7
Figure 19-4. If
19-5