Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 503

15.9 Memory System Interface Examples
The following examples show how to connect and set up the UPM RAM array for two types of
DRAM—page mode DRAM and page mode extended data-out DRAM. The values used in these examples
apply to any UPM. UPMA is used in the page mode example and UPMB is used in the extended data out
example.
15.9.1 Page-Mode DRAM Interface Example
Figure 15-53 shows configuration for a 1-Mbyte, 32-bit wide memory system using four 256 Kbyte x 8-bit
DRAMs. Also shown is the physical connection between UPMA and the page mode DRAM. CS1 is
connected to all RAS and is controlled by the base register. BS_A[0:3] are mapped one-to-one to each of
the four DRAMs and are controlled by the UPM RAM word. The refresh rate is calculated based on a
25-MHz baud rate generator clock and the DRAM that requires a 512-cycle refresh every 8 ms.
MPC885
BS_A[0:3]
CS1
R/W
A[21:29]
D[0:31]
Follow these steps to configure a system for page mode DRAM:
1. Determine the system architecture, which includes the MPC885 and the memory system as shown
in the example in
2. Use the blank work sheet in
The timing diagrams in
the UPM860 or MCU unit applications for this. These applications are available at
http:/www.mot.com.
Freescale Semiconductor
MCM84256
256K x 8
BS_A0
MCM84256
256K x 8
BS_A2
Figure 15-53. Page-Mode DRAM Interface Connection
Figure 15-53.
Figure 15-70
Figure through Figure 15-62
MPC885 PowerQUICC Family Reference Manual, Rev. 2
RAS
BS_A1
CAS
W
A[0:8]
D[0:7]
D[0:7]
8-Bit
8-Bit
D[16:23]
D[0:7]
RAS
BS_A3
CAS
W
A[0:8]
to draw the timing diagrams for all the memory cycles.
can be used as a reference. Alternately, use
Memory Controller
MCM84256
256K x 8
RAS
CAS
W
A[0:8]
D[0:7]
D[8:15]
8-Bit
8-Bit
MCM84256
256K x 8
D[24:31]
D [0:7]
RAS
CAS
W
A[0:8]
15-63