Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 116

MPC885 Overview
1.7 Fast Ethernet Controller (FEC)
The FECs comply with the IEEE 802.3 specification for 10- and 100-Mbps connectivity. Full-duplex
100-Mbps operation is supported at system clock rates of 40 MHz and higher. A 25-MHz system clock
supports 10-Mbps operation or half-duplex 100-Mbps operation.
The implementation of bursting DMA reduces bus usage. Independent DMA channels for accessing BDs
and transmit and receive data minimize latency and FIFO depth requirements.
Transmit and receive FIFOs further reduce bus usage by localizing all collisions to the FEC. Transmit
FIFOs maintain a full collision window of transmit frame data, eliminating the need for repeated DMA
over the system bus when collisions occur. On the receive side, a full collision window of data is received
before any receive data is transferred into system memory, allowing the FIFO to be flushed in the event of
a runt or collided frame, with no DMA activity. However, external memory for buffers and BDs is
required; on-chip FIFOs are designed only to compensate for collisions and for system bus latency.
Independent TxBD and RxBD rings in external memory allow nearly unlimited flexibility in memory
management of transmit and receive data frames. External memory is inexpensive, and because BD rings
in external memory have no inherent size limitations, memory management can be easily optimized to
system needs.
1.8 Universal Serial Bus (USB)
The universal serial bus (USB) is an industry-standard extension to the PC architecture. The USB
controller on the MPC885 family supports data exchange between a wide range of simultaneously
accessible peripherals. Attached peripherals share USB bandwidth through a host-scheduled, token-based
protocol.
The USB physical interconnect is a tiered-star topology and the center of each star is a hub. Each wire
segment is a point-to-point connection between the host and a hub or function, or a hub connected to
another hub or a function. The USB transfers signal and power over a four-wire cable, and the signaling
occurs over two wires and point-to-point segments. The USB full-speed signaling bit rate is 12 Mbps.
Also, a limited-capability low-speed signalling mode is defined at 1.5 Mbps. Refer to the USB
Specification Revision 1.1 and Revision 2.0 for further details. They can be downloaded from
http://www.usb.org.
The MPC885 USB controller consists of a transmitter module, receiver module, and two protocol state
machines. The protocol state machines control the receiver and transmitter modules. One state machine
implements the function state diagram and the other implements the host state diagram. The USB
controller can implement a USB function endpoint, a USB host, or both for testing purposes (loop-back
diagnostics).
1.9 Communications Processor Module (CPM)
The MPC885 family is the next generation MPC8xx family of devices. Like its predecessor it implements
a dual-processor architecture, which provides both a high-performance, general-purpose processor for
application programming use as well as a special-purpose communication processor (CPM) uniquely
designed for communications applications.
1-18
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor