Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 223

7.3.1.2.5 Instruction Cache Invalidate All Command
The instruction cache invalidate all command (IC_CST[CMD] = 0b110) causes all unlocked, valid blocks
in the instruction cache to be marked invalid. As a result of the invalidate all command, the LRU bits of
all cache blocks point to either the unlocked way or to way 0 if both ways are unlocked. There are no error
cases for the invalidate all command.
The instruction cache performs the invalidate all command in one clock cycle.
7.3.2 Data Cache Control Registers
The MPC885 implements three special purpose registers (SPRs) to control the data cache: the data cache
control and status register (DC_CST), the data cache address register (DC_ADR), and the data cache data
port register (DC_DAT). The data cache can be disabled, invalidated, locked, or flushed by issuing the
appropriate commands to the data cache control registers (DC_CST, DC_ADR, and DC_DAT). Also, the
data cache control registers can be used to read the contents and tags of specific data cache blocks.
DC_CST[DFWT] can be used to force the data cache into write-through mode. DC_CST[LES] controls
true little-endian byte-ordering of the MPC885. See
The mtspr and mfspr instructions access the cache control registers, but they can be accessed only by
supervisor-level programs (that is, when MSR[PR] = 0). Any attempt to access these SPRs with a
user-level program (MSR[PR] = 1) results in a supervisor-level program exception.
The DC_CST register, shown in
0 1 2
Field DEN DFWT LES
Reset 0 0 0
R/W R R R
16
Field
Reset
R/W
SPR
Figure 7-6. Data Cache Control and Status Register (DC_CST)
Freescale Semiconductor
Appendix A, "Byte Ordering,"
Figure 7-6, has an SPR encoding of 568.
3 4 7
— CMD
— —
— R/W
MPC885 PowerQUICC Family Reference Manual, Rev. 2
8 9 10 11
— CCER1 CCER2
— 0 0
— R R
—
—
—
568
Instruction and Data Caches
for more information.
12 15
—
—
—
31
7-11