Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 940

Parallel I/O Ports
34.6.1 The Port E Registers
The five port E control registers determine whether a signal is open-drain, input or output, and
general-purpose or dedicated to a peripheral.
34.6.1.1 Port E Open-Drain Register (PEODR)
The port E open-drain register (PEODR) indicates when the port signals are configured in a normal or
wired-OR configuration. Bits 14 and 15 of PEODR are not implemented. PEODR is cleared by system
reset.
0
Field
Reset
R/W
Addr
16 17
Field OD16 OD17 OD18 OD19 0D20 0D21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31
Reset 0 0
R/W R/W R/W R/W
Addr
This register is affected by HRESET and SRESET.
Bits Name
0–15 — Reserved
16–31 OD n Port E open-drain configuration.
0 The I/O signal is actively driven as an output.
1 The I/O signal is an open-drain driver. As an output, the signal is actively driven low. Otherwise,
it is three-stated.
34.6.1.2 Port E Data Register (PEDAT)
The Port E Data Register (PEDAT) always reflects the current status of each line. Reading the port E data
register (PEDAT) returns data to the signal, regardless of whether it is an input or output. This allows
output conflicts to be found on the signal by comparing the written data with the data on the signal. Data
written to PEDAT is latched; if the corresponding PEDIR bit is configured as an output, the latched value
is driven onto its respective signal. PEDAT can be read or written at any time and is not initialized. This
register is affected by HRESET and SRESET.
34-22
0000_0000_0000_0000
18 19 20 21 22
0 0 0 0 0
R/W R/W R/W R/W
Figure 34-19. Port E Open-Drain Register (PEODR)
Table 34-23. PEODR Bit Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
—
—
0xAD4
23 24 25 26 27
0 0 0 0 0
R/W R/W R/W R/W R/W
0xAD6
Table 34-23 describes PEODR bits.
Description
15
28 29 30 31
0 0 0 0
R/W R/W R/W R/W
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