Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 473

15.6.1 Requests
An internal or external master's request for a memory access initiates one of the following patterns:
• Read single-beat pattern (RSS)
• Read burst cycle pattern (RBS)
• Write single-beat pattern (WSS)
• Write burst cycle pattern (WBS)
These patterns are described in
A UPM periodic timer request pattern initiates a periodic timer pattern (PTS), as described in
Section 15.6.1.2, "UPM Periodic Timer Requests."
An exception (reset or machine check triggered by the assertion of TEA) occurring while another UPM
pattern is running initiates an exception condition pattern (EXS).
A special pattern in the RAM array is associated with each of these cycle types.
start addresses of these patterns in the UPM RAM, according to cycle type. MCR-initiated
commands, however, can initiate patterns starting at any of the 64 UPM RAM words.
Read Single-Beat Request
Read Burst Request
Write Single-Beat Request
Write Burst Request
Periodic Timer Request
Exception Condition Request
15.6.1.1 Internal/External Memory Access Requests
When an internal master requests a new access to external memory, the address and type of transfer are
compared to each valid bank defined in BRx. The value in BRx[MS] selects the UPM to handle the
memory access. The user must ensure that the UPM is appropriately initialized before a request.
External memory access requests are single-beat and burst reads and writes. A single-beat transfer
transfers one operand consisting of a single byte, half word, or word. A burst transfer transfers four words.
A single-beat cycle starts with one transfer start and ends with one transfer acknowledge. For 32-bit
accesses, the burst cycle starts with one transfer start but ends after four transfer acknowledges. A 16-bit
bus requires 8 transfer acknowledges; an 8-bit bus requires 16.
Freescale Semiconductor
Section 15.6.1.1, "Internal/External Memory Access Requests."
Array Index
Generator
Figure 15-32. RAM Array Indexing
MPC885 PowerQUICC Family Reference Manual, Rev. 2
RAM Array
RSS 0x00
RBS 0x08
WSS 0x18
WBS 0x20
PTS 0x30
EXS 0x3C
Memory Controller
Figure 15-32 shows the
RUN
64 RAM
Words
15-33