Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 368

External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Name
Reset
PE19 Hi-Z
L1TXDB
MII2-TXEN
RMII2-TXEN
PE18 Hi-Z
SMTXD1
MII2-TXD3
PE17 Hi-Z
TIN3
CLK5
BRGO3
SMSYN1
MII2-TXD2
PE16 Hi-Z
L1RCLKB
CLK6
MII2-TXCLK
RMII2-REFCL
K
PE15 Hi-Z
TGATE1
MII2-TXD1
RMII2-TXD1
PE14 Hi-Z
MII2-TXD0
RMII2-TXD0
TCK Hi-Z
DSCK
TMS Pulled up
TDI Pulled up
DSDI
TDO Low
DSDO
3
TRST Pulled up
MII1_CRS Hi-Z
MII_MDIO Hi-Z
MII1_TXEN Low
12-38
Number Type
R6 Bidirectional General-Purpose I/O Port E Bit 19
(optional: L1TXDB—Transmit data output for the serial interface TDMb
open-drain) MII2-TXEN—Media-independent interface 2, transmit enable
RMII2-TXEN—Reduced media-independent interface 2, transmit
enable
M5 Bidirectional General-Purpose I/O Port E Bit 18
(optional: SMTXD1—SMC1 transmit data output
open-drain) MII2-TXD3—Media-independent interface 2, transmit data 3
T8 Bidirectional General-Purpose I/O Port E Bit 17
(optional: TIN3—Timer 3 external clock input
open-drain) CLK5—One of eight clock inputs that can be used to clock SCCs
and SMCs
BRGO3—Output clock of BRG3
SMSYN1—SMC1 external sync input
MII2-TXD2—Media-independent interface 2, transmit data 2
U6 Bidirectional General-Purpose I/O Port E Bit 16
(optional: L1RCLKB—Receive clock for the serial interface TDMb.
open-drain) CLK6—One of eight clock inputs that can be used to clock SCCs
and SMCs
MII2-TXCLK—Media-independent interface 1, transmit clock
RMII2-REFCLK—Reduced media-independent interface 1,
reference clock
T7 Bidirectional General-Purpose I/O Port E Bit 15
TGATE1—Timer 1/timer 2 gate signal
MII2-TXD1—Media-independent interface 2, transmit data 1
RMII2-TXD1—Reduced media-independent interface 2, transmit
data 1
P8 Bidirectional General-Purpose I/O Port E Bit 14
MII2-TXD0—Media-independent interface 2, transmit data 0
RMII2-TXD0—Reduced media-independent interface 2, transmit
data 0
R13 Input Provides clock to scan chain logic or for the development port
logic
T14 Input Controls the scan chain test mode operations
T13 Input Input serial data for either the scan chain logic or the development
port and determines the operating mode of the development port
at reset
P13 Output Output serial data for either the scan chain logic or the
development port
U14 Input Test reset for the JTAG scan chain logic
U10 Input MII1_CRS —Media-independent interface 1, carrier receive
sense
M13 Bidirectional MII_MDIO —Media-independent interface management data
U5 Output MII1_TXEN —Media-independent interface 1, transmit enable
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor