Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 971

36.7 Serial ATM Operation
The SCCs running serial ATM operate independently of the physical interface standard used. The TDM
ports can be used with serial ATM to allow an easy connection to an E1 or T1 line interface device. It is
also possible to use an SCC directly through the NMSI.
In addition to the functions provided for UTOPIA operation, the serial ATM mode includes a transmission
convergence (TC) layer. The TC layer provides cell delineation, scrambling, idle cell generation or
filtering, and defines the interface characteristics to support E1/T1 or xDSL line interface devices.
36.7.1 Serial ATM Transmit Overview
The serial transmit process begins with the APC. The APC controls the ATM traffic of the transmitter
through a user-configured timer that defines the maximum outgoing bit rate. The APC uses each ATM
channel's specific traffic parameters to divide the total bit rate among the active channels. It can provide
CBR, VBR and UBR traffic services. ABR can also be supported through software manipulation of APC
parameters. The task of the APC is to define the next channel (or channels) to be transmitted. Refer to
Chapter 40, "ATM Pace Control,"
APC.
When operating in serial mode, transmit requests are internally generated by an SCC. The transmitter takes
the next channel from the transmit queue for the SCC. It then reads the channel-specific information from
the transmit connection table (TCT), and updates the TCT. The cell data is then copied from the transmit
buffer to an internal buffer where the CRC32 and HEC are calculated, the cell header is appended, and
scrambling is optionally performed. After the cell assembly process, the cell is moved into the SCC's
transmit FIFO for transmission.
The transmitter appends the trailer of the CPCS-PDU in the last cell of an AAL5 user frame. The
CPCS-PDU consists of the frame length (which is calculated during the frame transmit), the CPCS-UU
and CPI fields from the TxBD, and cell padding as required. The transmitter also sets PTI[1] in the header
of the last cell of the frame. An interrupt can be optionally generated to declare the end of a transmit frame.
When transmitting AAL0 cells, the ATM controller copies the cell (except the HEC) from the channel's
cell transmit buffer. The ATM controller optionally generates CRC10 for the cell payload and places the
result at the end of the payload. This feature is used to support OAM CRC10 per ITU specification I.610.
The transmitter sends idle cells (with idle cell contents defined by the user) if there are no channel numbers
in the transmit queue or if the current channel in the transmit queue has no valid buffers. An idle cell will
continue to be sent each time the APC schedules this channel in the transmit queue until either a buffer is
made ready or a
TRANSMIT DEACTIVATE CHANNEL
controller commands, refer to
36.7.2 Serial ATM Receive Overview
The serial receive process starts after the receiver becomes synchronized with the incoming cells and can
perform cell delineation. A receive request is then generated by an SCC. The receiver copies the first word
from the SCC to the dual-port RAM (DPR). The receiver translates the header address (VCI/VPI/PTI) to
a channel number through either a look-up table in dual-port RAM, address compression tables in external
Freescale Semiconductor
for additional information about the operation and programming of the
command is issued. For additional information about ATM
Section 39.4, "Port-to-Port (PTP) Switching."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
ATM Overview
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