Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 146

Powerquicc family

Table of Contents

The MPC8xx Core

Instruction Flow

As many as one instruction per clock cycle is fetched into the four-entry instruction queue (IQ). The branch

processing unit (BPU) predicts the outcome of branch instructions and in some cases, resolves whether the

branch is taken.

Fetch (maximum one instruction per clock cycle)

Dispatch (maximum one instruction per clock cycle)

Retire (maximum one instruction per clock cycle)

Non-branch instructions reaching IQ0 are dispatched to the execution units at an optimal rate of one

instruction per clock cycle. An instruction cannot be dispatched unless it can also take a position in the

six-entry completion queue (CQ).

All branch instructions, including unconditional branch instructions, reaching IQ0 must also take a

position in the completion queue. This allows program order to be maintained, it ensures a precise

execution model, and it allows branch instructions to be used as breakpoints.

All instructions enter the CQ along with processor state information that can be affected by the

instruction's execution. Executed arithmetic instructions pass their results both to rename buffers and to

the architected registers (typically GPRs), but to ensure program order, instructions remain in the CQ until

they can be retired.

If an exception occurs before the instruction can be retired, any results are removed from the rename buffer

and GPR and the instruction is flushed from the completion queue, along with subsequent instructions that

have not executed or have not dispatched.

This information is used to enable out-of-order completion of instructions and ensure a precise exception

model. An instruction can be retired after all instructions ahead of it have retired and it updates the

architected destination registers without taking an exception.

shows general instruction flow.

Instruction Queue

Completion Queue

Figure 3-2. Instruction Flow Conceptual Diagram

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Freescale Semiconductor