Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 458

Memory Controller
This register is not affected by HRESET or SRESET.
Bits Name
0–31 MA Contains a 32-bit address to be output on the address bus if AMX = 0b11. See
"RAM Words."
15.4.8 Memory Periodic Timer Prescaler Register (MPTPR)
The memory periodic timer prescaler register (MPTPR) defines the divisor of the external bus clock used
as the memory periodic timer input clock. See
Bit
0
Field
Reset
R/W
Addr
Figure 15-14. Memory Periodic Timer Prescaler Register (MPTPR)
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–7 PTP Periodic timers prescaler. Contains the division factor defined below.
001x xxxx Divide by 2.
0001 xxxxDivide by 4.
0000 1xxx Divide by 8.
0000 01xx Divide by 16.
0000 001x Divide by 32.
0000 0001 Divide by 64.
All other values are reserved.
8–15 — Reserved, should be cleared.
15.5 General-Purpose Chip-Select Machine (GPCM)
The GPCM allows a glueless and flexible interface between the MPC885, SRAM, EPROM, FEPROM,
ROM devices, and external peripherals. The GPCM contains three basic configuration register
groups—BRx, ORx, and MSTAT.
The GPCM provides a CS signal for memory bank activation, WE signals for write cycles for each byte
written to memory, and OE signals for read cycles.
SRAM device and the MPC885.
15-18
Table 15-9. MAR Field Description
Section 14.3, "Clock Signals."
PTP
0000_001x
(IMMR & 0xFFFF0000) + 0x17A
Table 15-10. MPTPR Field Descriptions
Figure 15-15
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 15-9 describes MAR fields.
Description
7 8
0000_0000
R/W
Table 15-10
Description
shows a simple connection between an
Section 15.6.4.1,
15
—
describes MPTPR fields.
Freescale Semiconductor