Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 306

System Interface Unit
0
Field
Reset
R/W
Addr
16
Field
Reset
R/W
Addr
Table 10-12 describes SIVEC fields.
Bits Name
0–7 INTC Interrupt code. Indicates the highest priority pending interrupt; equals the interrupt number times 4,
as shown in
8–31 — Reserved, should be cleared.
SIVEC[INTC] represents the unmasked interrupt source of the highest priority level. When SIVEC is read
as a byte, a branch table can be used in which each entry contains one instruction (branch). The interrupt
code is the interrupt number times 4, which allows indexing into the table. When read as a half word, each
entry can contain a full routine of up to 256 instructions; see
10-18
INTC
xx11_11xx_xxxx_xxxx
(IMMR & 0xFFFF0000) + 0x01C
xxxx_xxxx_xxxx_xxxx
(IMMR & 0xFFFF0000) + 0x01E
Figure 10-13. SIU Interrupt Vector Register (SIVEC)
Table 10-12. SIVEC Field Descriptions
Table 10-7.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
7 8
R
—
R
Description
Figure 10-14 and
15
—
31
Table 10-7.
Freescale Semiconductor