Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 215

0
20
Set0
Set1
Set254
Set255
MMU
Hit0
Each instruction cache block contains four contiguous words from memory that are loaded from a
four-word boundary; that is, bits A[30–31] of the logical (effective) addresses are zero. As a result, cache
blocks are aligned with page boundaries. Also, address bits A[20–27] provide the index to select a set, and
bits A[28–29] select a word within a block. The tags consist of the high-order physical address bits
PA[0–19]. Address translation occurs in parallel with set selection (from A[20–27]).
The instruction cache implements a single state bit for each cache block that indicates whether the cache
block is valid or invalid. The MPC885 does not support snooping of the instruction cache. All memory is
Freescale Semiconductor
Data Effective Address
Way0
Tag0 w0 w1 w2 w3
w2
Tag1 w0 w1 w2 w3
Tag254 w0 w1 w2 w3
Tag255 w0 w1 w2 w3
20
COMP
HIT
Figure 7-1. MPC885 Instruction Cache Organization
MPC885 PowerQUICC Family Reference Manual, Rev. 2
19 20
8 Bits
8
. . . .
Tag0
.. . .
Tag1
L
R
U
A
r
r
a
y
. . . .
Tag254
. . . .
Tag255
20
128
COMP
Hit1
Bidirectional Multiplexer 2 -> 1
128
To/From Block Buffer
Instruction and Data Caches
27 28 29 30 31
2
Reserved
2
Word Select
Way1
w0 w1 w2 w3
w2
w0 w1 w2 w3
w0 w1 w2 w3
w0 w1 w2 w3
128
7-3