Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 574

Powerquicc family

Table of Contents

Communications Processor

This register is affected by HRESET and SRESET.

CP reset command. Set by the core and cleared by the CP. Executing this command clears RST

and FLG within two general system clocks. The CPM reset routine takes approximately 60

clocks, but CPM initialization can start immediately after this command is issued. Use RST to

reset the registers and parameters for all the channels (USB, SCCs, SMCs, SPI, I

as well as the CPM and RISC timer table. RST does not, however, affect the serial interface or

parallel I/O registers.

0 No reset issued

1 Reset issued

Reserved. Should be cleared.

OPCODE Operation code for the core-issued CP commands. See

CH_NUM Channel number. Defines the specific sub-block on which the command is to operate. Some

sub-blocks share channel number encodings if their commands are mutually exclusive.

001x Reserved

0101 SPI/IDMA2/RISC timers

011x Reserved

101x Reserved

111x Reserved

Reserved., should be cleared.

Command semaphore flag. Set by the core and cleared by the CP.

0 CP is ready for a new command.

1 CP is currently processing a command—cleared when the command is done or after reset.

A given CP command opcode may have different meanings, or may not apply, depending on which

channel (sub-block) the command targets.

INIT RX AND TX

Table 18-6. CPCR Field Descriptions

Table 18-7. CP Command Opcodes

(UART/Transparent)

INIT RX AND TX

INIT RX PARAMS

INIT TX PARAMS

MPC885 PowerQUICC Family Reference Manual, Rev. 2

describes CPCR fields.

INIT RX AND TX

INIT RX AND TX

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