Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 625

Bits Name
13, 29 GM x Grant mode for TDMa/b
0 GCI/SCIT mode. The GCI/SCIT D channel grant mechanism for transmission is supported
internally. The grant is signalled by one bit of the Rx frame and is marked by setting
SIRAM[CSEL] to 111 to assert an internal strobe. See
1 IDL mode. A grant mechanism is supported if the corresponding SICR[GR n ] are set. The grant
is a sample of the L1GR x signal while L1TSYNC x is asserted. This grant mechanism implies
the IDL access controls transmission on the D channel. See
the IDL
L1RQa. (The RTS4 function is still available on port D.)
Note that if GMb = 1, then the RTS3 signal on ports B and C functions as L1RQb. (The RTS3
function is still available on port D.)
14–15, TFSD x Transmit frame sync delay for TDMa/b. Determines the delay between the Tx sync and the first
30–31 bit of the Tx frame. If CRT x is set, the Rx sync is used as the common sync, and the TFSD x bits
refer to this common sync.
00 No bit delay. The first bit of the frame is sent on the same clock as the sync.
01 1-bit delay
10 2-bit delay
11 3-bit delay
The following series of figures show timing examples.
changing the delay from frame sync to data valid.
L1CLK
(CE=0)
L1SYNC
(FE=1)
Data
One Clock Delay from Sync Latch to First Bit of Frame
Figure 20-14. One Clock Delay from Sync to Data ( x FSD = 01)
L1CLK
(CE=0)
L1SYNC
(FE=1)
Data
Freescale Semiconductor
Table 20-5. SIMODE Field Descriptions (continued)
Interface."Note that if GMa = 1, then the RTS4 signal on ports B and C functions as
Bit-0 Bit-1 Bit-2
Bit-0 Bit-1 Bit-2
No Delay from Sync Latch to First Bit of Frame
Figure 20-15. No Delay from Sync to Data ( x FSD = 00)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Section 20.2.6.2.2, "SCIT Mode
Section 20.2.5.2, "Programming
Figure 20-14 and Figure 20-15
End of Frame
Bit-3 Bit-4 Bit-5
Bit-3 Bit-4 Bit-0
Serial Interface
show the effects of
Bit-0
Bit-1 Bit-2
20-19