Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 601

Level-sensitive mode maximizes IDMA channel bandwidth for peripherals requiring high transfer rates.
For external peripherals that generate a pulsed transfer signal for each data operand, edge-sensitive
requests should be used.
19.3.7.2.1 Level-Sensitive Requests
Setting RCCR[DRnM] makes the corresponding IDMA channel level-sensitive to requests. DREQ is
sampled at rising edge of the clock. The peripheral requests service by asserting DREQ and leaving it
asserted as long as it needs service.
Each time the IDMA controller issues a bus cycle either to read or write the peripheral, it asserts SDACK
to acknowledge the original transfer request on DREQ. The IDMA channel continues moving data in
back-to-back DMA cycles until DREQ is negated. To ensure the correct number of DMA transfers are
performed, the peripheral must negate DREQ while the IDMA is acknowledging the last data move, that
is, while SDACK is asserted. DREQ is sampled on the same rising edge on which TA is sampled to
terminate the current cycle.
19.3.7.2.2 Edge-Sensitive Requests
Clearing RCCR[DRnM] makes the corresponding IDMA channel edge-sensitive to requests. The edge
sensitivity is further qualified to detect either any edge or falling edges only as programmed in
PCINT[EDM15] and PCINT[EDM14] for DREQ0 and DREQ1, respectively; see
C Interrupt Control Register (PCINT)."
In edge-sensitive mode, an IDMA channel moves one data operand per request. DREQ is sampled at each
rising edge of the clock. When IDMA detects a request on DREQ, the request is considered pending and
remains pending until it is processed. Subsequent requests on DREQ are ignored until the pending request
is acknowledged.
19.3.8 IDMA Transfers—Dual-Address and Single-Address
Once an IDMA channel successfully arbitrates for the bus, it begins the transfer. An IDMA channel has
the same bus cycle timing as the other internal masters.
The IDMA controller supports both dual- and single-address transfers. The dual-address transfer consists
of a source read and a destination write—a memory/memory or memory/peripheral transfer. A
single-address transfer, also called fly-by, consists of one external read or write bus cycle—a
memory/peripheral transfer.
19.3.8.1 Dual-Address (Dual-Cycle) Transfer
The IDMA channels can operate in a dual-address transfer mode in which data is first read using the source
pointer and placed in internal storage. The data operand is then packed onto the bus and written to the
address given by the destination pointer. The read and write transfers can take several bus cycles each
because of differences in the source and destination operand sizes. The dual-address read and write cycles
are described below.
• Dual-address source read—SAPR drives the address bus, SFCR drives the address type, and
DCMR drives the size control. Data is read from the memory or peripheral and placed in internal
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SDMA Channels and IDMA Emulation
Section 34.4.1.5, "Port
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