Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 427

Powerquicc family

Table of Contents

GCLK1 Divided by 1

GCLK2 Divided by 1

GCLK1 Divided by 2

GCLK2 Divided by 2

GCLK1 Divided by 4

GCLK2 Divided by 4

Figure 14-6. Divided System Clocks (GCLK x ) Timing Diagram

Memory Controller and External Bus Clocks

(GCLK1_50, GCLK2_50, CLKOUT)

The MPC885 provides the capability to run the external bus and memory controller at a lower frequency

than the internal modules. This capability is provided by the external bus frequency dividers. The external

bus clocks GCLK1_50 and GCLK2_50 are derived from GCLK1 and GCLK2, as determined by the

SCCR[EBDF]. SCCR[EBDF] is cleared by HRESET, and thus GCLK1_50 and GCLK2_50 default to

GCLK1 and GCLK2. The timing relationship between GCLKx and GCLKx_50 is shown in

Figure 14-7. Memory Controller and External Bus Clocks Timing

Freescale Semiconductor

Diagram for EBDF=0 and EBDF=1

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Clocks and Power Control