Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 622

Serial Interface
0
Field
Reset
R/W
Addr
This register is affected by HRESET but is not affected by SRESET.
fields.
Bits Name
0–3 — Reserved, should be cleared.
4 ENb Enable TDMb.
0 TDMb is disabled. SI RAM and TDM routing are in a state of reset; all other SI functions still
operate.
1 TDMb is enabled.
5 ENa Enable TDMa.
0 TDMa is disabled. SI RAM and TDM routing are in a state of reset; all other SI functions still
operate.
1 TDMa is enabled.
6–7 RDM RAM division mode. Defines the SI RAM partitioning based on the number of TDM channels
supported and whether dynamic changes are needed.
00 Static TDMa with 64 entries apiece for Rx and Tx routing. (TDMb cannot be used.)
01 Dynamic TDMa with 32 entries apiece for current-route and shadow Rx routing and 32 apiece
for current-route and shadow Tx routing. (TDMb cannot be used.)
10 Static TDMa and TDMb with 32 entries apiece for the Rx routing and 32 apiece for Tx routing.
11 Dynamic TDMa and TDMb with 16 entries apiece for current-route and shadow Rx routing and
16 apiece for current-route and shadow Tx routing.
Note that after setting SIGMR[ENx], data from the transmit buffers does not immediately appear at the
TDM transmit pin with the first frame because the SCCs require start-up clocking at initialization. Expect
a number of bytes of idle (typically 10–15) depending on the size of the frame and number of time slots
routed to the particular SCC.
20-16
3
—
Figure 20-12. SI Global Mode Register (SIGMR)
Table 20-4. SIGMR Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
4 5
ENb ENa
0
R/W
0xAE4
Table 20-4
Description
6 7
RDM
describes the SIGMR
Freescale Semiconductor