Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 536

PCMCIA Interface
16.4.5 PCMCIA Base Registers 0–7 (PBR0–PBR7)
Setting a bit in the PBR, shown in
Bit 0
Field
Reset
R/W
Addr (IMMR & 0xFFFF0000) + 0x080 (PBR0); 0x088 (PBR1); 0x090 (PBR2); 0x098 (PBR3); 0x0A0 (PBR4); 0x0A8
This register is not affected by HRESET or SRESET.
Bits Name
0–31 PBA
16.4.6 PCMCIA Option Register 0–7 (POR0–POR7)
The POR, shown in Figure
size, and defines the region, slot, write protection, and validation.
0
Field BSIZE
Reset
R/W
Addr (IMMR & 0xFFFF0000) + 0x084 (POR0); 0x08C (POR1); 0x094 (POR2); 0x09C (POR3); 0x0A4 (POR4);
16
Field PSST
Reset
R/W
Addr (IMMR & 0xFFFF0000) + 0x086 (POR0); 0x08E (POR1); 0x096 (POR2); 0x09E (POR3); 0x0A6 (POR4);
16-14
Figure 16-5, enables the corresponding interrupt.
(PBR5); 0x0B0 (PBR6); 0x0B8 (PBR7)
Figure 16-7. PCMCIA Base Register (PBR)
Table 16-12. PBR Field Descriptions
PCMCIA base address. Compared to the address on the address bus to determine if a
PCMCIA window is being accessed by an internal bus master. PBA is used with
POR[BSIZE].
16-8, as the manipulation of timing, provides the address mask for the bank
4 5
0x0AC (POR5); 0x0B4 (POR6); 0x0BC (POR7)
19 20
PSL
0x0AE (POR5); 0x0B6 (POR6); 0x0BE (POR7)
Figure 16-8. PCMCIA Option Register 0–7 (POR0–POR7)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
...
PBA
—
R/W
Table 16-12 describes the PBR.
Description
11
—
Undefined
R/W
24 25 26
PPS PRS
Undefined
R/W
31
12 15
PSHT
28 29 30 31
PSLOT WP PV
Freescale Semiconductor