Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 362

External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Name
Reset
IP_A4 Hi-Z
IP_A5 Hi-Z
IP_A6 Hi-Z
IP_A7 Hi-Z
ALE_B See
DSCK Table 12-3
IP_B[0:1] See
IWP[0:1] Table 12-3
VFLS[0:1]
OP0 Low
OP1 Low
OP2 Hi-Z
MODCK1
STS
OP3 Hi-Z
MODCK2
DSDO
12-32
Number Type
D2 Input Input Port A 4—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
E3 Input Input Port A 5—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface
F4 Bidirectional Input Port A 6—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
C2 Input Input Port A 7—This input signal is monitored by the MPC875 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
C8 Bidirectional Address Latch Enable B—This output is asserted when the
three-state MPC875 initiates an access to a region under the control of the
PCMCIA socket B interface.
Development Serial Clock—This input is the clock for the debug
port interface.
B8, D9 Bidirectional Input Port B 0-1—The MPC875 senses these inputs; their values
and changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Instruction Watchpoint 0-1—These outputs report the detection of
an instruction watchpoint in the program flow executed by the
core.
Visible History Buffer Flushes Status—The MPC875 outputs
VFLS[0:1] when program instruction flow tracking is required.
They report the number of instructions flushed from the history
buffer in the core.
B6 Output Output Port 0—This output signal is generated by the MPC875 as
a result of a write to the PGCRA register in the PCMCIA interface.
C6 Output Output Port 1—The MPC875 generates these outputs as a result
of a write to the PGCRA register in the PCMCIA interface.
B5 Bidirectional Output Port 2—This output is generated by the MPC875 as a
result of a write to the PGCRB register in the PCMCIA interface.
Mode Clock 1—Input sampled when PORESET is negated to
configure PLL/clock mode.
Special Transfer Start—The MPC875 drives this output to indicate
the start of an external bus transfer or an internal transaction in
show-cycle mode.
B2 Bidirectional Output Port 3—This output is generated by the MPC875 as a
result of a write to the PGCRB register in the PCMCIA interface.
Mode Clock 2—This input is sampled at the PORESET negation
to configure the PLL/clock mode of operation.
Development Serial Data Output—Output data from the debug
port interface.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor