Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 381

External Bus Interface
The master can stop driving the data bus as soon as it samples TA asserted on the rising edge of CLKOUT.
On a read cycle the master accepts the data bus contents as valid at the rising edge of CLKOUT in which
TA is sampled asserted.
13.4.2.1 Single-Beat Read Flow
The basic read cycle begins with a bus arbitration, followed by the address transfer, then the data transfer.
The following flow and timing diagrams show the handshakes applicable to the fixed transaction protocol.
Figure 13-4 maps the flow of a single-beat read cycle.
MASTER SLAVE
Bus Request (BR)
Receives Bus Grant (BG) from arbiter
Asserts Bus Busy (BB) if no other master is driving
Asserts Transfer Start (TS)
Drives address and attributes
Receives Address
Returns data
Asserts Transfer Acknowledge (TA)
Receives data
Figure 13-4. Basic Flow Diagram of a Single-Beat Read Cycle
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 13-7