Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 318

Reset
• External soft reset
• Internal soft reset
— Debug port soft reset
All of these reset sources are fed into the reset controller and, depending on the source of the reset, different
actions are taken. The reset status register reflects the last source to cause a reset.
11.1.1 Power-On Reset
Power-on reset of the MPC885 is accomplished through the PORESET input signal. The PORESET signal
must be externally asserted following initial power-up. When PORESET is asserted the MODCK bits are
sampled to configure SCCR[PTDIV] and SCCR[PTSEL]. The phase-locked loop multiplication factor is
configured for default operation in the PLPRCR register. When PORESET is negated, the MODCK values
are sampled and internally latched. To ensure proper operation, PORESET should be asserted for a
minimum of 3 µs. After sampling the assertion of PORESET, the MPC885 enters the power-on reset state
and stays there until both of the following events occur:
• The internal PLL enters the lock state and the system clock is active.
• PORESET is negated.
After the negation of PORESET or PLL lock, the core enters the state of internal initiated HRESET and
continues driving both HRESET and SRESET for 512 clock cycles. After 512 cycles elapse, the
MPC885's configuration is sampled from the data signals and the core stops internally asserting both
HRESET and SRESET. To ensure prompt negation, external pull-up resistors should be provided to drive
HRESET and SRESET high. After HRESET and SRESET are internally negated, a 16-cycle period passes
before the presence of an external (hard/soft) reset is sampled. See
information.
11.1.2 External Hard Reset
The hard reset (HRESET) signal is a bidirectional, active low, open-collector I/O signal. The MPC885 can
only sample an external assertion of HRESET if it occurs while the MPC885 is not internally asserting
HRESET. While HRESET is asserted, SRESET is also asserted.
11.1.3 Internal Hard Reset
When the core initiates a hard reset it asserts the HRESET and SRESET signals for 512 cycles. After 512
clock cycles the data signals are sampled, initial configuration is established, and the core stops driving
the HRESET and SRESET signals. Following the negation of HRESET and SRESET a 16-cycle period
passes before an external hard or soft reset is sampled. Note that external pull-up resistors should be
provided to drive HRESET and SRESET high. See
The causes of internal hard reset are as follows:
• Software watchdog reset
• Checkstop reset
• Debug port hard reset
11-2
Section 11.3.1, "Hard Reset,"
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 11.3.1, "Hard Reset,"
for more information.
Freescale Semiconductor
for more