Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 278

Powerquicc family

Table of Contents

Instruction Execution Timing

Writeback Arbitration

9-2, the addic instruction is dependent on the mulli result. Because the single-cycle instruction

sub has priority on the writeback bus over the mulli, the mulli writeback is delayed one clock and causes

a bubble in the execute stream.

Read + Execute

In this example, the addic instruction is dependent on sub rather than on mulli. Although the writeback

of the mulli is delayed two clocks, there is no bubble in the execution stream.

mulli r12,r4,3

sub r3,r15,3

addic r4,r3,1

Read + Execute

Private Writeback Bus Load

9-4, lwz and xor write back in the same clock since they use the writeback bus in two different

ticks (a tick = 1/4 of a processor clock).

Figure 9-2. Writeback Arbitration Timing—Example 1

Figure 9-3. Writeback Arbitration Timing—Example 2

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Freescale Semiconductor