Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 300

System Interface Unit
IRQ[0-4]
IRQ[6-7]
Edge
Detector
If programmed to generate interrupts, the software watchdog timer generates a nonmaskable system reset
interrupt (NMI) to the core. Asserting the external IRQ0 pin generates an NMI as well. Note that the core
takes the system reset interrupt vector when an NMI is asserted and jumps to the external interrupt vector
when any other interrupt is asserted by the interrupt controller. Each external IRQ pin is assigned a priority
level. Each SIU internal interrupt source, generated by the CPM's interrupt controller (CPIC), can be
assigned by the software to one of eight additional internal interrupt priority levels, described in
Chapter 35, "CPM Interrupt Controller."
Section 10.5.3.1, "Nonmaskable Interrupts—IRQ0 and SWT,"
from other IRQ signals, and how the operation is configurable through SIU registers.
10.5.2 Priority of Interrupt Sources
There are seven external IRQ pins (IRQ0 is essentially nonmaskable, although in a limited sense it can be
masked as shown in Table
an internal interrupt) and eight interrupt levels. Asserting IRQ0 causes an NMI. The other 15 interrupt
sources assert a single interrupt request to the core (the external interrupt).
priorities.
10-12
SIU
Decrementer
Selector
Timebase
Periodic
Interrupt Timer
PCMCIA
CPM
Debug
Figure 10-7. MPC885 Interrupt Structure
10-8, and IRQ5 is not an external interrupt pin but can be assigned to generate
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Software
Watchdog Timer
NMI
Generator
IRQ0
Level 7
Level 6
Level 5
Level 4
Interrupt
Controller
Level 3
Level 2
Level 1
Level 0
describes how IRQ0 operates differently
Table 10-7
NMI
Decrementer
MPC8xx
CORE
External
Interrupt
Debug
shows interrupt
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