Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 982

Buffer Descriptors and Connection Tables
Table 37-2 describes the ATM TxBD fields.
Offset from
Bits
TBD_PTR
0x00 0
1
2
3
4
5
6
7–12
37-8
Table 37-2. ATM TxBD Field Descriptions
Name
R Ready. Determines whether the data buffer is ready for transmission.
0 The data buffer associated with this BD is not ready for transmission. The
CPU core is free to manipulate this BD and its associated data buffer. The CP
clears this bit after the buffer has been sent or after an error condition is
encountered.
1 The data buffer, which has been prepared for transmission by the user, has
not been sent or is currently being sent. This BD and its buffer should not be
modified by the CPU core.
— Reserved, should be cleared during initialization.
W Wrap. Determines whether this is the final BD in the table.
0 This is not the last BD in the TxBD table.
1 This is the last BD in the TxBD table. The next time this channel is scheduled
to send data, the first BD in the channel's TxBD table (the BD pointed to by
the channels's TCT[TBASE] address) will be used. The number of TxBDs in
the table is programmable and is limited by the 256K memory space for all
the transmit channels.
I Interrupt. Enables interrupts generated when the contents of the buffer have
been sent.
0 No interrupt is generated after the buffer has been transmitted.
1 The TXB bit is set in an entry in the interrupt queue after the buffer has been
sent.
L Last in frame (AAL5). Set by the user for the last buffer in an AAL5 frame.
0 This is not the last buffer in the transmit frame.
1 This is the last buffer in the current transmit frame.
OAM This bit is valid only in AAL0 buffers. Programmed by the user to distinguish
between user cells and non user cells. This bit is used by the performance
monitoring (PM) process; see the ITU-T recommendation I.610.
0 User cell
1 Non - user cell
CM Continuous mode. Note that TxBD[R] is cleared if an error occurs during
transmission, regardless of CM.
0 Normal operation.
1 The CP does not clear TxBD[R] after this BD is closed, allowing the buffer to
be resent the next time the CP accesses this BD.
— Reserved, should be cleared during initialization.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor