Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 480

Memory Controller
Bit Name
16 G3T4 General-purpose line 3 timing 4. Defines the state of GPL3 during phase 1–3.
0 Asserted at the falling edge of GCLK2_50.
1 Negated at the falling edge of GCLK2_50.
17 G3T3 General-purpose line 3 timing 3. Defines the state of GPL3 during phase 4.
0 Asserted at the falling edge of GCLK1_50.
1 Negated at the falling edge of GCLK1_50.
18 G4T4/ General-purpose line 4 timing 4/delay time 3. The function is determined by M x MR[GPL x 4DIS].
DLT3
G4T4 If M x MR defines UPWAITx/GPL_x4 as an output (GPL_x4), this bit functions as G4T4:
0 The value of GPL4 at the falling edge of GCLK2_50 will be 0.
1 The value of GPL4 at the falling edge of GCLK2_50 will be 1.
DLT3 If M x MR[GPL x 4DIS] = 1, UPWAITx is chosen and this bit functions as DLT3.
0 The data bus should be sampled at the rising edge of GCLK2_50 for a read in this cycle.
1 The data bus should be sampled at the falling edge of GCLK2_50 for a read in this cycle.
19 G4T3/ W General-purpose line 4 timing 3/wait enable. Function depends on the value of M x MR[GPL x 4DIS].
AEN
If M x MR[GPL x 4DIS] = 0, G4T3 is selected.
G4T3
0 The value of GPL4 at the falling edge of GCLK1_50 will be 0.
1 The value of GPL4 at the falling edge of GCLK1_50 will be 1.
W AEN If M x MR[GPL x 4DIS] = 1, WAEN is selected.
0 The UPWAITx function is disabled.
1 The logical value of the UPM-controlled external signals are frozen when UPWAITx is asserted.
UPWAITx is sampled on the falling edge of GCLK2_50. See Figure 15-45. for more information.
20 G5T4 General-purpose line 5 timing 4. Defines the state of GPL5 during phase 1–3.
0 The value of GPL5 at the falling edge of GCLK2_50 will be 0.
1 The value of GPL5 at the falling edge of GCLK2_50 will be 1.
21 G5T3 General-purpose line 5 timing 3. Defines the state of GPL5 during phase 4.
0 The value of GPL5 at the falling edge of GCLK1_50 will be 0.
1 The value of GPL5 at the falling edge of GCLK1_50 will be 1.
22–23 — Reserved, should be cleared.
24 LOOP Loop. The first RAM word in the RAM array where LOOP is 1 is recognized as the loop start word.
The next RAM word where LOOP is 1 is the loop end word. RAM words between the start and end
are defined as the loop. The number of times the UPM executes this loop is defined in the
corresponding loop field of the M x MR.
0 The current RAM word is not the loop start word or loop end word.
1 The current RAM word is the start or end of a loop.
See Section 15.6.4.5, "Loop Control (LOOP)."
25 EXEN Exception enable. If an external device asserts TEA or RESET, EXEN allows branching to an
exception pattern at the exception start address (EXS) at a fixed address in the RAM array.
0 The UPM continues executing the remaining RAM words.
1 The current RAM word allows a branch to the exception pattern after the current cycle if an
exception condition is detected. The exception condition can be an external device asserting
TEA, HRESET, or SRESET.
15-40
Table 15-14. RAM Word Bit Settings (continued)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor