Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 275

8.10.2 Locking TLB Entries
Four entries in each TLB can be made unavailable to the replacement algorithm; thus by configuring the
TLB replacement counters, the user can lock translation entries into them.
As shown in Figure 8-25, setting MI_CTR[RSV4I] or MD_CTR[RSV4D], configures the TLB
replacement counter to select only from the first 28 entries in each TLB. Those fields also affect the tlbia
instruction as described later. Replacement counters are cleared after a tlbia instruction executes.
ITLB_INDX decrements after an ITLB reload; DTLB_INDX decrements after a DTLB reload.
ITLB
0
1
2
•
•
•
26
27
28
29
30
31
8.10.3 Loading Locked TLB Entries
The process of loading a single reserved entry in the TLB is as follows:
1. Disable the TLB by clearing MSR[IR] or MSR[DR] as needed.
2. Clear MI_CTR[RSV4I] (MD_CTR[RSV4D]).
3. Invalidate the EA of the reserved page by using tlbia or tlbie.
4. Set MI_CTR[ITLB_INDX] (MD_CTR[DTLB_INDX]) to the appropriate value (between 27 and
31).
5. Load Mx_EPN with the effective page number, the ASID of the reserved page, and set EV.
6. Run software tablewalk code to load the appropriate entry into the translation lookaside buffer. See
Section 8.10.1.1, "Translation Reload
7. Repeat steps 4–6 to load other TLB entries.
8. Set MI_CTR[RSV4I] (MD_CTR[RSV4D]).
8.10.4 TLB Invalidation
Executing tlbie invalidates TLB entries that hit, including reserved entries. Note that EA[0–21] is used in
the comparison because segment registers as defined by the PowerPC architecture are not implemented.
Although for entries with pages larger than 4 Kbytes, some lower bits of the effective page number are
ignored. The ASID value in the entry is ignored for the purpose of matching an invalidate address; thus,
multiple entries can be invalidated if they have the same effective address and different ASID values.
Freescale Semiconductor
RSV4I = 1
RSV4I = 0
Figure 8-25. Configuring the TLB Replacement Counter
Examples."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Memory Management Unit
DTLB
0
1
2
•
•
•
26
27
28
RSV4D = 1
29
30
31
RSV4D = 0
8-33