Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 495

at the falling edge of CLKOUT upon encountering the WAEN bit being set in the UPM word. The
UPM stays in that state until UPWAIT is negated. After UPWAIT is negated, the UPM continues
executing from the next entry to the end of the pattern (LAST bit is set).
• The external TA solution (GPCM)—The bus interface module asserts TA to the memory controller
when it can sample data.
15.7.2 Slow Devices Example
Assume the CPU initiates a read cycle from a device whose access time exceeds the maximum allowed by
the user programming model.
• The wait solution (UPM)—The CPU generates a read access from the slow device. The device in
turn asserts the wait signal as long as the data is not ready. The CPU samples data only after the
wait signal is negated.
• The external TA solution (GPCM)—The CPU generates a read access from the slow device, which
must generate the synchronous TA when it is ready.
15.8 External Master Support
The memory controller supports internal and external bus masters. Accesses from the core or the CPM are
considered internal; accesses from an external bus master are external. External bus master support is
available only if enabled in the SIU module configuration register (SIUMCR), described in Section 10.4.2.
There are two types of external bus masters:
• Synchronous bus masters synchronize with CLKOUT and may or may not use the MPC885
memory controller to access a slave.
• Asynchronous bus masters use an address strobe signal (AS) that handshakes with the MPC885
memory controller to access a slave device or bypass the memory controller to perform the slave
access.
15.8.1 Synchronous External Masters
Synchronous masters initiate a transfer by asserting TS. A[0:31], RD/WR, BURST, and TSIZ must be
stable before the rising edge of CLKOUT after TS is asserted and until the last TA is negated. Because the
external master operates synchronously with the MPC885, meeting setup and hold times for all inputs
associated with the rising edge of CLKOUT is critical. To support synchronous mode using the memory
controller, SIUMCR[SEME] must be set. When TS is asserted, the memory controller compares the
address with each of its valid banks. If a match is found, control signals to the slave are generated and TA
is supplied to the external master. If SEME = 0, the memory controller is bypassed and the external
synchronous master must provide control signals to the slave. See
15.8.2 Asynchronous External Masters
Asynchronous masters initiate transfers by driving the address bus and asserting AS. A[0:31], RD/WR,
and TSIZ must have a proper setup time before AS is asserted. To support asynchronous mode,
SIUMCR[AEME] must be set. The memory controller synchronizes AS assertion to its internal clock and
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Memory Controller
Figure 15-47.
15-55