Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 376

External Bus Interface
the level recognized by the MPC885 is unpredictable; however, the MPC885 always resolves the latched
level to either a logical high or low before using it. For deterministic operation, all input signals must obey
the protocols described in this chapter in addition to meeting input setup and hold times.
Input Hold Time
Input Setup Time
Clock
Signal
Sample
Window
Figure 13-1. Input Sample Window
TSIZ0 and TSIZ1 indicate the number of bytes remaining to be transferred during an operand cycle
(consisting of one or more bus cycles) and are driven with the address type signals at the beginning of a
bus cycle. These signals are valid at the rising edge of the clock in which the transfer start signal (TS) is
asserted.
13.3 Bus Interface Signal Descriptions
Figure 13-3 shows the bus signals for the MPC885.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
13-2 Freescale Semiconductor