Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 895

Bits Name
2 W Wrap (last BD in table).
0 Not the last BD in the RxBD table.
1 Last BD in the RxBD table. After this buffer is used, the CPM receives incoming data using the
BD pointed to by RBASE (top of the table). The number of BDs in this table is determined only by
the W bit.
3 I Interrupt.
0 No interrupt is generated after this buffer is full.
1 The I2CER[RXB] is set when the CPM fills this buffer, indicating that the core needs to process
the buffer. The RXB bit can cause an interrupt if it is enabled.
4 L Last. The I
0 This buffer does not contain the last character of the message.
1 This buffer holds the last character of the message. The I
data is placed into the associated buffer, or because of a stop or start condition or an overrun.
5–13 — Reserved and should be cleared.
14 OV Overrun. Set when a receiver overrun occurs during reception. The I
after the received data is placed into the associated buffer.
15 — Reserved and should be cleared.
2
32.7.1.2 I C Transmit Buffer Descriptor (TxBD)
Transmit data is arranged in buffers referenced by TxBDs in the TxBD table. The first word of the TxBD,
shown in Figure 32-14, contains status and control bits.
0 1
Offset + 0 R —
Offset + 2
Offset + 4
Offset + 6
2
Table 32-10 describes I
Bits Name
0 R Ready
0 The buffer is not ready to be sent. This BD or its buffer can be modified. The CPM clears R after
the buffer is sent or an error occurs.
1 The buffer is ready for transmission or is being sent. The BD cannot be modified once R is set.
1 — Reserved and should be cleared.
2 W Wrap (last BD in TxBD table)
0 Not the last BD in the table
1 Last BD in the table. After this buffer is used, the CPM transmits data using the BD pointed to by
TBASE (top of the table). The number of BDs in this table is determined only by the W bit.
Freescale Semiconductor
2
Table 32-9. I C RxBD Status and Control Bits (continued)
2
C controller sets L.
2 3 4 5
W I L S
2
Figure 32-14. I C Transmit Buffer Descriptor (TxBD)
C TxBD status and control bits.
2
Table 32-10. I C TxBD Status and Control Bits
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
2
C controller sets L after all received
6
—
Data Length
Tx Buffer Pointer
Description
2
I C Controller
2
C controller updates this bit
12 13 14 15
NAK UN CL
32-13