Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 90

Powerquicc family

Table of Contents

Used to express an undefined numerical value

NOT logical operator

AND logical operator

OR logical operator

Acronyms and Abbreviations

contains acronyms and abbreviations used in this document. Note that the meanings for some

acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not

be intuitively obvious.

Analog-to-digital

Arithmetic logic unit

Asynchronous transfer mode

Buffer descriptor

Built-in self test

Branch processing unit

Basic rate interface.

Content-addressable memory

Conférence Européene des Administrations des Postes et des Télécommunications (European

Conference of Postal and Telecommunications Administrations)

Communications processor

Communications processor module

Condition register

Cyclic redundancy check

Count register

Data address breakpoint register

Data address register

Decrementer register

Direct memory access

Digital phase-locked loop

Dynamic random access memory

Data translation lookaside buffer

Table ii. Acronyms and Abbreviated Terms

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Freescale Semiconductor