Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 455

Bits Name
13–14 DS x
15 —
16–18 G0CL x [0–2] General line 0 control x . Selects the address line output to the internal GPL0 signal in the
19 GPL x 4DIS
20–23 RLF x
24–27 WLF x
28–31 TLF x
15.4.5 Memory Command Register (MCR)
The memory command register (MCR) is used during UPM initialization to read and write the contents of
the UPM RAM. It also allows commands to be issued that stimulate UPM routine execution. This
capability lets the CPU perform special memory operations in addition to standard read/write and periodic
timer service operations. An example of this is software execution of a special UPM pattern to initialize
SDRAM.
Freescale Semiconductor
Table 15-6. M x MR Field Descriptions (continued)
Disable timer period. Guarantees a minimum time between accesses to the same memory
bank if it is controlled by the UPM x . This function can be used to guarantee a minimum RAS
precharge time. The TODT bit in the RAM array turns on the disable timer and, when
expired, the UPM x allows the machine access to issue a memory pattern to the same
region. An access attempted before the timer expires (as signalled by TS assertion) has wait
states inserted before the UPM pattern runs. Accesses to other chip-selects serviced by this
UPM are unaffected by this timer. The maximum disable period is four clock cycles. If more
than 4 cycles are required, they must be added explicitly in the UPM RAM words.
00 1-cycle disable period
01 2-cycle disable period
10 3-cycle disable period
11 4-cycle disable period
Reserved, should be cleared.
special case where the functionality is enabled in the G0L and G0H bits of the UPM RAM
word.
000 = A12
001 = A11
010 = A10
011 = A9
GPL x 4 output line disable. Determines whether UPWAIT x /GPL_ x 4 behaves as the GPL4
output controlled the UPM RAM word, or an input signal used to dynamically insert wait
states into UPM patterns.
0 = UPWAIT x /GPL_ x 4 is defined as GPL_ x 4.
1 = UPWAIT /GPL_ x 4 is defined as UPWAIT x .
X
Read loop field x . Specifies (in binary) the number of times a loop defined in the UPM x RAM
word is executed for a burst read or single-beat read cycle. (0001 = 1 time, 0010 = 2 times,
..., 1111 = 15 times; note that 0000 = 16 times.)
Write loop field x . Specifies the number of times a loop defined in the UPM x RAM word is
executed for a burst- or single-beat write cycle. (0001 = 1 time, 0010 = 2 times, ..., 1111 =
15 times; note that 0000 = 16 times.)
Timer loop field x . Specifies the number of times a loop defined in the UPM x RAM word is
executed for a periodic timer service. (0001 = 1 time, 0010 = 2 times, ..., 1111 = 15 times;
note that 0000 = 16 times.)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
100 = A8
101 = A7
110 = A6
111 = A5
Memory Controller
15-15