Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 151

Address
Increment
To execute multiple/string instructions and unaligned accesses, the LSU increments the EA to access all
necessary data. This allows the LSU to execute unaligned accesses without stalling the master instruction
pipeline.
3.6.3.1 Executing Load/Store Instructions
When load or store instructions are dispatched, the LSU determines if all of the operands are available.
These operands include the following:
• Address register operands
• Source data register operands (for store instructions)
• Destination data registers (for load instructions)
• Destination address GPRs (for load/store with update instructions)
If all operands are available, the LSU takes the instruction and enables the sequencer to issue a new
instruction. Using a dedicated interface, the LSU notifies the integer unit of the need to calculate the EA.
All load/store instructions are executed and finished in order. If no prior instructions are in the address
queue, the load/store operation is issued to the data cache when the instruction executes. Otherwise, if prior
instructions remain whose addresses have not been issued to the data cache, the instruction's address and
data are placed in their respective queues. For load/store with update instructions, the destination address
register is written back on the following clock cycle, regardless of the address queue's state.
Freescale Semiconductor
Integer
Unit
Address
32-Bit
Queue
and
D-Cache/D-MMU
32-Bit
Interface
Figure 3-5. LSU Functional Block Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
GPRs
Integer Integer
Load Data Store Data
32-Bit 32-Bit
LOAD/STORE
UNIT
Integer
32-Bit
Data Queue
32-Bit
The MPC8xx Core
CORE
3-11