Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 161

• Condition register logical instructions perform logical operations on specified CR bits.
• CR0 can be the implicit result of an integer instruction.
• A specified CR field can indicate the result of an integer compare instruction.
Note that branch instructions are provided to test individual CR bits.
4.1.1.1.2 Condition Register CR0 Field Definition
For all integer instructions, when the CR is set to reflect the result of the operation (that is, when Rc = 1),
and for addic., andi., and andis., CR0[0–2] are set by an algebraic comparison of the result to zero;
CR0[3] is copied from XER[SO]. For integer instructions, CR[0–3] reflects the result as a signed quantity.
The CR bits are interpreted as shown in
into CR0[0–3] is undefined.
CR0 Bit
0 Negative (LT). Set when the result is negative.
1 Positive (GT). Set when the result is positive (and not zero).
2 Zero (EQ). Set when the result is zero.
3 Summary overflow (SO). This is a copy of the final state of XER[SO] at the completion of the instruction.
Note that CR0 may not reflect the true (that is, infinitely precise) result if overflow occurs.
4.1.1.1.3 XER
Figure 4-2 shows XER bit assignments. Settings are based on the final result produced by executing an
instruction.
0 1
Field SO OV CA
Reset
R/W
16
Field
Reset
R/W
Freescale Semiconductor
Table 4-3. If any portion of the result is undefined, the value placed
Table 4-3. Bit Settings for CR0 Field of CR
2 3
0000_0000_0000_0000
—
0000_0000_0000_0000
Figure 4-2. XER Register
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
—
R/W
24 25
R/W
MPC8xx Core Register Set
15
31
BCNT
4-3