Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 450

Memory Controller
These registers are affected by HRESET but are not affected by SRESET.
Bits Name
0–16 BA Base address. Compared to A[0:16]to determine if a memory bank controlled by the memory
controller is being accessed by an internal or external bus master. Used with OR x [AM].
17–19 AT Address type. Can be used to limit accesses to the memory bank to a certain address space type,
AT[0:2]. Note that for internal bus masters, AT[0:2] are sampled from the bus. For external bus
masters, AT[0:2] are not sampled on the external bus and instead default to 0b100. Used with
OR x [ATM].
20–21 PS Port size. Specifies the port size of the memory region. After system reset, the value of BR0[PS]
depends on BPS in the hard reset configuration word, described in
Configuration Word."
00 32-bit port size.
01 8-bit port size.
10 16-bit port size.
11 Reserved.
22 — Reserved, should be cleared.
23 WP Write-protect. Can be used to restrict write accesses within the address range of a BR.
0 Both read and write accesses are allowed.
1 Only read accesses are allowed. The memory controller does not assert CSx and TA on write
cycles to this memory bank. Attempting to write to the memory bank causes MSTAT[WPER] to
be set. The write access is not terminated by the memory controller; however, it is terminated by
a TEA assertion from the bus monitor if the bus monitor is enabled.
24–25 MS Machine select. Selects the machine for handling memory operations.
00 GPCM.
01 Reserved.
10 UPMA.
11 UPMB.
26–30 — Reserved, should be cleared.
31 V Valid. Indicates that the contents of the BR x and OR x are valid. The reset value of BR0[V] depends
on BDIS in the hard reset configuration word, described in Section 11.3.1.1.
0 This bank is invalid. An attempt to access this region can cause a bus monitor timeout.
1 This bank is valid. The CS signal does not assert until V is set.
15-10
Table 15-3. BR x Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 15-3
Description
Section 11.3.1.1, "Hard Reset
describes BRx fields.
Freescale Semiconductor