Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 320

Powerquicc family

Table of Contents

External Soft Reset

When an external SRESET is asserted, the core starts driving the SRESET signal. After 512 clock cycles

the debug port configuration is sampled from the DSDI and DSCK signals and the core stops driving the

SRESET signal. Once the core negates SRESET 16 clock cycles must elapse before the external soft reset

signal is again sampled.

The soft reset (SRESET) signal is also a bidirectional, active low, open-collector I/O signal. The MPC885

can detect an external assertion of SRESET only if it occurs while the MPC885 is not internally asserting

HRESET or SRESET.

Internal Soft Reset

The JTAG and debug ports can initiate an internal soft reset, resulting in the assertion of the SRESET

signal. After 512 cycles, the core negates SRESET and the debug port configuration is sampled from the

DSDI and DSCK signals. Once the core negates SRESET, 16 clock cycles must elapse before the external

soft reset signal is sampled.

Soft Reset Sequence

shows the reset sequence following an internal or external soft reset event.

Internal or external

SRESET asserted

16 clocks expire

• DSDI is sampled to determine

clocked or self-clocked mode

Reset Status Register (RSR)

The 32-bit reset status register (RSR) is memory-mapped into the MPC885 system interface unit register

map and receives its default reset values at power-on reset. This register is also affected by HRESET and

Internal initiated

• SRESET assert

• The time counter is set to 512

Timer expires (after 512 clocks)

• Sample debug port configuration from DSDI and DSCK pins

• Negate SRESET

• Wait for 16 clocks

External SRESET still asserted

16 clocks expire

Start normal execution

(From system reset interrupt exception vector)

Figure 11-2. Soft Reset Sequence

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Freescale Semiconductor