Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 462

Memory Controller
As Figure 15-20 shows, the timing for CS is the same as for the address lines. The strobes for the
transaction are supplied by OE or WE, depending on the transaction direction (read or write). ORx[CSNT]
controls the timing for the appropriate strobe negation in write cycles. When this attribute is asserted, the
strobe is negated one quarter of a clock before the normal case. For example, when ACS = 00 and CSNT
= 1, WE is negated one quarter of a clock earlier, as shown in
= 1, WE and CS are negated one quarter of a clock earlier, as shown in
Address
Figure 15-19. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0)
15-22
MPC885
Address
CS
OE
WE
Data
Figure 15-18. GPCM Memory Device Interface
Clock
TS
TA
CS
WE
OE
Data
MPC885 PowerQUICC Family Reference Manual, Rev. 2
MEMORY
Address
CE
OE
W
Data
15-19. When ACS ≠ 00 and CSNT
Figure
Figure
CSNT = 1
15-20.
Freescale Semiconductor