Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 658

Serial Communications Controllers
0
Offset + 0
Offset + 2
Offset + 4
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For frame-oriented protocols, a message can reside in as many buffers as necessary. Each buffer has a
maximum length of 65,535 bytes. The CP does not assume that all buffers of a single frame are currently
linked to the BD table. The CP does assume, however, that the unlinked buffers are provided by the core
in time to be sent or received; otherwise, an error condition is reported—an underrun error when sending
and a busy error when receiving.
Dual-Port RAM
SCC TxBD
SCC RxBD
SCC RxBD Table
(RBASE)
SCC TxBD Table
(TBASE)
In all protocols, BDs can point to buffers in the internal dual-port RAM. However, because internal RAM
is used for descriptors, buffers are usually put in external RAM, especially if they are large. Usually, the
internal U bus transfers data to the buffer.
The CP processes TxBDs in a straightforward manner. Once the transmit side of an SCC is enabled, it
starts with the first BD in that SCC TxBD table. Once the CP detects that the R bit is set in the TxBD, it
starts processing the buffer. The CP detects that the BD is ready when it polls the R bit or when the user
writes to the TODR. After data from the BD is put in the Tx FIFO, if necessary the CP waits for the next
21-12
High-Order Buffer Pointer
Low-Order Buffer Pointer
Figure 21-6. SCC Buffer Descriptors (BDs)
Figure 21-7 shows the SCC BD table and buffer structure.
Status and Control
Table
Buffer Pointer
Table
Status and Control
Data Length
Pointer
Buffer Pointer
Pointer
Figure 21-7. SCC x Buffer Descriptor and Buffer Structure
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Status and Control
Data Length
Tx Buffer Descriptors
Data Length
Rx Buffer Descriptors
15
External Memory
Tx Buffer
Rx Buffer
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