Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 280

Instruction Execution Timing
xor r4,r3,r5
ori r7,r8,1
GCLK1
Fetch
Decode
Read + Execute
Writeback
L Address Drive
L Data
Cache Address
Load Writeback
E Address
E Data
9.1.6 Branch Instruction Handling
In Figure 9-7 the lwz instruction accesses internal memory with one wait state. The IQ and parallel
operation of the BPU allows the two bubbles caused by the bl issue and execution to overlap the two
bubbles caused by the load. Issuing bl causes a bubble because it does no work.
lwz r12,64 (SP)
sub r3,r12,3
addic r4,r14,1
bl func
...
func:
mulli r5,r3,3
addi r4,3(r0)
GCLK1
Fetch
Decode
Read + Execute
Writeback
L Address Drive
L Data
Load Writeback
Branch Decode
Branch Execute
9-4
lwz sub addic
lwz sub
lwz sub
lwz
Figure 9-6. Full Completion Queue Timing
lwz sub addic
lwz sub
lwz
lwz
Figure 9-7. Branch Folding Timing
MPC885 PowerQUICC Family Reference Manual, Rev. 2
and xor ori
addic and xor
addic and Bubble
sub addic and
lwz
lwz
bl Bubble
Bubble Bubble
lwz
lwz
bl
bl
Bubble xor
lwz
lwz
lwz
mulli addi
addic mulli
sub addic mulli
sub addic
Freescale Semiconductor
xor